Individual die packaged as separate components offer little inherent anti-tamper protection when sensitive information needs to be passed between the components. In the past, to improve the protection of the die and the interfaces between the die, individual die have been directly applied to a single substrate and packaged as a multi-chip module (MCM) system-in-package (SiP). Next an over-coating or over-mold was applied to the MCM to improve the security of the sensitive data internal to the MCM (on-die and between the die). In some instances these over-coatings and over-molds detrimentally impacted the cost, manufacturability and reliability of the MCM. In other instances these over-coatings and over-molds did not significantly improve the security of the MCM. Additionally, this packaging technique could result in a rather large module ranging in size from over a square inch to several square inches.
An alternate approach is to combine all of the individual die into a single ASIC as a system-on-chip (SoC) design. SoC designs offer a high degree of inherent anti-tamper protection and size reduction, but may present significant risk to the design and development team. The combination of all the functions needed to create the SoC may be extremely complex. There may be incompatibilities between the memory needed or other features of the die, and the die manufacturers capabilities. Additionally, a single error in the ASIC may cost $250,000 (for a metalization layer change) to $1,000,000 (for a complete respin) to correct.
Another alternative approach is to stack the die within a single package. Current stacked die packaging techniques address size reduction, but most offer little inherent anti-tamper protection. Packaging options for stacked die packages come in many forms. The two basic options for intra-package interconnect is bond wiring and bumping (flip chip packaging). Wire-bonding may connect the die to a laminate substrate using small wires, from the top, active face of the die down to the substrate. Multiple die are then stacked on top of each other and wire bonded down to a substrate. A flip chip package may basically include a thin core laminate substrate with the die inverted and soldered down using solder bumps on the die. The active face of the die may be directly connected to the substrate using a small solder bump. Multiple substrates are then stacked on top of each other either by ball grid array attachment or by wire bonding them down to a single bottom substrate. Wafer level flip chip technology is being developed. This technique refers to the direct attaching of a flip chip die to the active surface of a custom designed ASIC.